1. Field of the Invention
The present invention relates to an oscillation circuit capable of reducing power consumption when a power supply voltage is high.
2. Description of the Related Art
In a non-volatile memory, for example, an EEPROM, which allows data to be electrically erased, written, or read out, there is a need to apply a high voltage, which is the same as or higher than a power supply voltage VDD, to a selected memory cell in the erasing and writing operation. A desired high voltage is generated through use of a charge pump circuit configured to boost an input voltage.
An output current of a booster circuit using the charge pump circuit is expressed by Expression (1):
                    IOUT        =                                            CCP              ×              VCLK                        TCLK                    =                      fCLK            ×            CCP            ×            VDD                                              (        1        )            where TCLK represents an oscillation cycle of a clock signal of an oscillation circuit, fCLK represents an oscillation frequency of the output clock signal of the oscillation circuit, CCP represents a capacitance of a capacitor of the charge pump circuit, and VCLK represents an amplitude of the clock signal, that is, the power supply voltage VDD.
Based on Expression (1), an output current IOUT supplied to the memory cell is in proportion to the power supply voltage VDD. Thus, the output current IOUT is excessively supplied when the power supply voltage is high. As a result, there is a problem in that current consumption and power consumption are largely increased.
In order to solve this problem, the following technology is proposed (for example, see Japanese Patent No. 3553508).
FIG. 5 is a circuit diagram for illustrating an example of a related-art oscillation circuit.
The related-art oscillation circuit is a ring oscillator circuit in which odd stages of inverter circuits 3, each of which includes a PMOS transistor and an NMOS transistor that are connected to each other in series, are cascade connected to form a ring. Constant current elements 2 are each connected to each of the inverter circuits 3. Each of the constant current elements 2 are connected to a power supply circuit 1.
Charges Q that are charged to and discharged from a gate capacitance Cg of each of the inverter circuits 3 forming the ring oscillator circuit are expressed by Expression (2).Q=Cg×VDD=IBIAS×t  (2)where IBIAS represents a charge and discharge current, and t represents charge and discharge time.
By deforming Expression (2), the charge and discharge time t and the oscillation frequency fCLK are expressed by Expression (3) and Expression (4), respectively.
                    t        =                                            C              g                        ×            VDD                    IBIAS                                    (        3        )            
                    fCLK        =                              1                          2              ×              t                                =                      IBIAS                          2              ×                              C                g                            ×              VDD                                                          (        4        )            
In a power supply voltage region sufficient for the power supply circuit 1 to stably operate, the charge and discharge current IBIAS is determined by the constant current elements 2. The charge and discharge current IBIAS is considered to be constant regardless of the power supply voltage VDD. Thus, the gate capacitance Cg of each of the inverter circuits 3 and the charge and discharge current IBIAS are considered to be constants. From Expression (3) and Expression (4), the charge and discharge time t is in proportion to the power supply voltage VDD, and the oscillation frequency fCLK is in inverse proportion to the power supply voltage VDD.
Through use of the oscillation circuit 10 configured as above, the oscillation frequency fCLK may be reduced when the power supply voltage VDD rises. The output current IOUT may be suppressed, to thereby enable low current consumption and low power consumption.
However, in recent years, the power supply voltage of a semiconductor device is increasingly reduced. Therefore, in a semiconductor device having the booster circuit, it is required to operate at a low voltage while maintaining low current consumption and low power consumption.